Semiconductor Technology for Ultra-Large Scale Integrated Circuits and Thin Film Transistors VI (ULSIC vs TFT 6)
Oxide semiconductor based charge trap device for vertically integrated NAND flash memory
May 21-25, 2017
Vertically integrated NAND flash memory (V-NAND) is the data storage component of modern hand-held electronic devices, which will also critically contribute to the futuristic devices for internet of things. The present V-NAND adopts thin poorly crystallized Si as the channel layer to minimize the cell-to-cell and device-to-device variability. However, the very low carrier (electron) mobility of such channel (only ~0.03 cm2/V·sec) deteriorates the device performance (write and read speed), which will eventually limit the maximum stackable number of device layers even if the various process-related issues for V-NAND fabrication are solved. An alternative channel material with amorphous structure and higher carrier mobility, therefore, is necessary for further development of V-NAND, and amorphous oxide semiconductor (AOS), such as In2Ga2ZnO7 (IGZO) or ZnSnO3 (ZTO), is an appealing contender for such application. Figure 1 shows a schematic diagram (left panel) and achieved memory performance (middle and right panels) of a double-layer stacked integrated charge trap flash (CTF) where the ZTO channel was grown by metal-organic chemical vapor deposition (MOCVD), and other Sicontaining materials were grown by standard Si processes. Both top and bottom CTF devices showed feasible memory performances in the drain current – gate voltage sweep mode with sufficiently high memory window, which were also stable at 85oC guaranteeing the 10-year-retention time. However, the program time, estimated in pulse program/erase mode, was impractically long (order of sec.) suggesting that there must be significant improvements in material stack or process conditions. The relatively thick tunneling oxide (4nm SiO2) may seriously limit the electron tunneling, but thinner SiO2 could not guarantee sufficient retention time. In the presentation, the material and integration strategies to improve such problem will be discussed. These strategies include AOS material variation (IGZO vs. ZTO), process method (sputtering vs. MOCVD), and integration schemes (tunneling oxide thickness and thermal treatments), of which details are dependent on the AOS material and process methods
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Cheol Seong Hwang, "Oxide semiconductor based charge trap device for vertically integrated NAND flash memory" in "Semiconductor Technology for Ultra-Large Scale Integrated Circuits and Thin Film Transistors VI (ULSIC vs TFT 6)", Yue Kuo (Texas A&M University, USA) Olivier Bonnaud (University of Rennes I, France) Eds, ECI Symposium Series, (2017). https://dc.engconfintl.org/ulsic_tft_6/21