Semiconductor Technology for Ultra-Large Scale Integrated Circuits and Thin Film Transistors VI (ULSIC vs TFT 6)
Atomic layer deposition: Low temperature process well adapted to ULSI and TFT technologies
May 21-25, 2017
The high k dielectrics is an important materials to be integrate in future Ultra Large Scale Integration (ULSI) and future TFT technology. Indeed, to keep on the Moore's Law curve, the reduction of silicon oxide (SiO2) thickness still required, but this reduction is hindered by tunneling current leakage limit. Consequently, it is important to replace SiO2 by another materials with high dielectric constant. The use of this material in manufacturing of gate dielectric in Thin-film transistor (TFT) and in Complementary Metal Oxide Semiconductor (CMOS) will increase gate capacitance with maintaining a low leakage current. Titanium dioxide is a good candidate due to its high dielectric constant in its rutile crystalline phase (180).This rutile structure is obtained at low temperature (250°C) by ALD deposition when TiO2 is deposited on ruthenium dioxide (RuO2) layer thanks to the small lattice mismatch between these two materials.
Ahmad Chaker, Pierre Szkutnik, Patrice Gonon, Christophe Vallée, and Ahmad Bsiesy, "Atomic layer deposition: Low temperature process well adapted to ULSI and TFT technologies" in "Semiconductor Technology for Ultra-Large Scale Integrated Circuits and Thin Film Transistors VI (ULSIC vs TFT 6)", Yue Kuo (Texas A&M University, USA) Olivier Bonnaud (University of Rennes I, France) Eds, ECI Symposium Series, (2017). https://dc.engconfintl.org/ulsic_tft_6/28