Semiconductor Technology for Ultra-Large Scale Integrated Circuits and Thin Film Transistors VI (ULSIC vs TFT 6)
Large scale graphene integration for silicon technologies
May 21-25, 2017
The main guarantor of success for silicon based semiconductor research and industry was the availability and continuous improve of wafer fabrication processes for large scale integration. New material integration in a stable and reliable silicon process platform has to face several challenges. Graphene as a 2D material is considered as a material with formidable properties. This can enable new functionalities and performance improvements in a large variety of applications. Using graphene devices in microelectronics requires beside appropriate performances certain techniques for large scale fabrication of graphene which are currently not yet in place. In this paper we present recent progress of process platform developments to enable wafer scale integration in a silicon cmos platform. Synthesis of graphene on silicon cmos compatible substrates are considered to fulfill a basic request for the integration of graphene related devices in a silicon environment with no risk of metallic cross contamination. We present recent results of graphene synthesis on Ge(100) and Ge (110). Therefore chemical vapor deposition (CVD) methods are used to realize Ge/Si substrates followed by a CVD graphene synthesis at ~890°C (1,2). Due to silicon diffusion inside germanium certain germanium thickness is required to allow the subsequent graphene process. We present high quality graphene on a 200mm silicon wafers with high uniformity, a 2D/G ratio of ~3 and low D mode over the entire 200mm wafer measured by Raman spectroscopy (Figure 1). To enable a selective graphene synthesis on a 200mm wafer we discuss first approaches of graphene growth on patterned germanium island.
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Andreas Mai, Marco Lisker, Mindaugas Lukosius, and Grzegorz Lupina, "Large scale graphene integration for silicon technologies" in "Semiconductor Technology for Ultra-Large Scale Integrated Circuits and Thin Film Transistors VI (ULSIC vs TFT 6)", Yue Kuo (Texas A&M University, USA) Olivier Bonnaud (University of Rennes I, France) Eds, ECI Symposium Series, (2017). https://dc.engconfintl.org/ulsic_tft_6/35