Trapping mechanism of charge trap capacitor with Al2O3/High- k/Al2O3 multilayer
May 21-25, 2017
Charge trap flash memories with Al2O3/High-k/Al2O3 multilayer have been considered to reduce leakage current and improve electrical properties under low operation voltage for further device scaling down capability [1, 2]. In case of charge trap capacitor with SiO2/SiN/Al2O3 multilayer, the several mechanism have been proposed to recognize where injected electron is trapped. For example, the injected electrons are piled up in a center of SiNcharge trap layer (SiN-CTL) or interface between SiO2 tunneling layer (TL) and SiN-CTL or other interface between SiN-CTL and Al2O3-blocking layer (AlO-BL) . However, the trapping mechanism of the High-k-charge trap layer (High-k-CTL) is still not clear. In this paper, we focus on the trapping mechanism of High-k-CTLs, such as an amorphous (Ta/Nb)Ox (TNO-CTL), a crystallized ZrO2 (ZrO-CTL) and a ferroelectric HfZrOx (HZO-CTL), from the data of flatband voltage (Vfb) characteristics under program mode. Pt-gated charge trap capacitors with Al2O3/(Ta/NbOx)/Al2O3 (ATNA), Al2O3/ZrO2/Al2O3 (AZA), and Al2O3/HfZrOx/Al2O3 (AHZA) were prepared by atomic layer deposition and annealing processes. The thicknesses of the TNO, ZrO and HZO-CTLs were varied from 5 to 20 nm while Al2O3-tunneling layer (AlO-TL) and AlO-BL were kept to be 8 nm thickness.
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Toshihide Nabatame, "Trapping mechanism of charge trap capacitor with Al2O3/High- k/Al2O3 multilayer" in "Semiconductor Technology for Ultra-Large Scale Integrated Circuits and Thin Film Transistors VI (ULSIC vs TFT 6)", Yue Kuo (Texas A&M University, USA) Olivier Bonnaud (University of Rennes I, France) Eds, ECI Symposium Series, (2017). https://dc.engconfintl.org/ulsic_tft_6/7