Embedded DRAM using c-axis-aligned crystalline In-Ga-Zn oxide FET with 1.8V-power-supply voltage

Conference Dates

May 19-23, 2019


An embedded memory using c-axis aligned crystalline In-Ga-Zn oxide (CAAC-IGZO) FETs with an extremely low off-state current on the order of yoctoamperes (yA) (yocto- is a metric prefix denoting a factor of 10-24) is known as a potential next-generation memory [1][2]. A dynamic oxide semiconductor RAM (DOSRAM), where each memory cell is composed of one CAAC-IGZO FET and one capacitor, enables long data retention and long interval of refresh operations with an advantage of extremely low off-state current of the CAAC-IGZO FET. However, negative backgate voltage (Vbg) and word-line driving voltages of 0/3.3 V (VSSL/VDDH) had been required for an access transistor of the memory cell to satisfy high on-state current and low off-state current.

This work shows that DOSRAM operates with 1.8 V-power supply voltage by using a novel driving method.

Figure 1 shows Vg-Id performance of a CAAC-IGZO FET used as a cell transistor. The threshold voltage (Vth) of the CAAC-IGZO FET is controlled by changing a level of Vbg, whereas Vth of the Si FET is controlled by channel doping. Figure 2 shows a block diagram of a prototyped DOSRAM. The refresh rate in DOSRAM mainly depends on the leakage current of cell transistors. To reduce the refresh rate to once an hour, the off-state current of the cell transistors on a non-selected word line needs to be reduced to 200 zeptoamperes (zA) per FET (zepto- is a metric prefix denoting a factor of 10-21) or lower at 85C. The required Vbg is -7.0 V to achieve such an off-state current at Vg  0 V, for example. To obtain approx. 100 MHz-driving frequency, the required on-state current is at least several microamperes. The voltage level difference in the word line, VDDH  VSSL, is a factor that determines the on-state current, and in this work is fixed to 3.3 V so that the combination of Vbg and the word line voltage is optimized. The application of negative voltage to the word line enables the leakage current of the cell transistor to be maintained low even when Vbg is increased. For example, whereas the existing driving method meets the above off-state current value with Vbg  -7.0 V and the VSSL  0 V, the novel driving method meets the value with Vbg  0 V and VSSL  -1.5 V. In the novel driving method, VDDH  1.8 V. There has been a report of a reduction in leakage current of a memory cell by application of negative voltage to a top gate in DRAM using Si CMOS [3]. In contrast to it, DOSRAM including CAAC-IGZO FETs with L  60 nm has a leakage current of 200 zA or lower, which is 7-digit lower than that of the DRAM using Si CMOS, and enables longer data retention.

The evaluation results of the prototyped DOSRAM verify that a reduction in power-supply voltage from 3.3 V to 1.8 V is possible in terms of operation and data retention. This suggests a highly compatible and efficient configuration of an embedded DRAM and a logic circuit where signals can be transmitted with low VDD.


[1] S. H. Wu, et al., IEEE Symp. VLSI Tech., pp. 166-167, 2017.

[2] T. Ishizu, et al., IEEE Symp. VLSI Cir., pp. 162-163, 2017.

[3] F. Hamzaoglu et al., IEEE Journal of Solid-State Circuits, vol. 50, no. 1, pp. 150-157, Jan. 2015.

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