Title
Challenge of crystalline IGZO ceramics to silicon LSI - Its application to AI and displays
Conference Dates
May 19-23, 2019
Abstract
We found crystalline IGZO ceramics having a layered structure, a crystalline oxide semiconductor called c-axis-aligned crystalline In-Ga-Zn oxide (CAAC-IGZO) in 2009. Recent research has revealed that CAAC-IGZO exhibits a structure in a boundary region between amorphous and crystal structures [1]. We are convinced that CAAC-IGZO is a novel crystalline phase, as shown in Table 1.
A field effect transistor (FET) using the crystalline IGZO ceramics with L/W = 0.8μm/100mm exhibits an off leakage current of 6yA/μm (10-24A/μm) at 85°C, which is such a low current that FETs using Si, the dominant semiconductor material, cannot ever achieve [2]. In the display industry, FETs utilizing this feature have been increasingly mounted on panel backplanes and widely adopted in various products such as TVs and smartphones. CAAC-IGZO FETs have a high on/off ratio and thus are being applied also to the field of LSI; a 60nm-node prototype line for mass production started operating [3]. CAAC-IGZO FETs are effective for applications such as FPGA, GPU, and DRAM, and are now being developed to target image processors and artificial intelligence (AI).
CAAC-IGZO FETs are known to have mobility that does not deteriorate at high temperatures [5]. Figure 1 shows cutoff frequency (fT) of a CAAC-IGZO FET and a Si FET at varying temperatures. While there is a difference in fT of the Si FET between 27°C and 150°C, a change in fT between different temperature conditions is small in the CAAC-IGZO FET. Moreover, fT of the CAAC-IGZO FET is 33GHz, which is approximately 1/4 that of the Si FET (137GHz). These results demonstrate that the on-state current and field-effect mobility of the CAAC-IGZO FET do not decrease with increasing temperature.
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Recommended Citation
Shunpei Yamazaki, "Challenge of crystalline IGZO ceramics to silicon LSI - Its application to AI and displays" in "Semiconductor Technology for Ultra Large Scale Integrated Circuits and Thin Film Transistors VII (ULSIC VS TFT 7)", Yue Kuo, Texas A&M University, USA Junichi Murota, Tohoku University, Japan Yukiharu Uraoka, Nara Advanced Institute of Science and Technology, Japan Yasuhiro Fukunaka, Kyoto University, Japan Eds, ECI Symposium Series, (2019). https://dc.engconfintl.org/ulsic_tft_vii/42