Title
Reliability of flexible low temperature poly-silicon thin film transistor
Conference Dates
May 19-23, 2019
Abstract
This work reports the effect of mechanical stress-induced degradation in flexible low-temperature polycrystalline-silicon thin-film transistors. After 100,000 iterations of channel-width-direction mechanical compression at R=2mm, a significant shift of extracted threshold voltage and an abnormal hump at the subthreshold region were found. Simulation reveals that both the strongest mechanical stress and electrical field takes place at both sides of the channel edge, between the polycrystalline silicon and gate insulator. The gate insulator suffered from a serious mechanical stress and result in a defect generation in the gate insulator. The degradation of the threshold voltage shift and the abnormal hump can be ascribed to the electron trapping in these defects. In addition, this work introduced three methods to reduce the degradation cause by the mechanical stress, including the quality improvement of the gate insulator, organic trench structure and active layer with a wing structure.
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Recommended Citation
Ting-Chang Chang, Chih-Yang Lin, Yu-Ching Tsao, Shin-Ping Huang, Bo-Wei Chen, Yi-Ting Tseng, Mao-Chou Tai, Cheng-Hsien Wu, Po-Wen Chang, and Po-Hsun Chen, "Reliability of flexible low temperature poly-silicon thin film transistor" in "Semiconductor Technology for Ultra Large Scale Integrated Circuits and Thin Film Transistors VII (ULSIC VS TFT 7)", Yue Kuo, Texas A&M University, USA Junichi Murota, Tohoku University, Japan Yukiharu Uraoka, Nara Advanced Institute of Science and Technology, Japan Yasuhiro Fukunaka, Kyoto University, Japan Eds, ECI Symposium Series, (2019). https://dc.engconfintl.org/ulsic_tft_vii/43