Devices in advanced technology nodes: Application-specific characterization
May 21-25, 2017
Growing requirements for higher performance with lower power consumption and higher density, as outlined in ITRS’15 and IRDS’17, drive aggressive device dimensional scaling combined with introduction of new semiconductor materials and ultra-thin multi-layer dielectric stacks. Inter-materials interaction in these structures, enhanced by high temperature fabrication processes, causes atomic diffusion across the interfaces and facilitates formation of defects, which may affect device performance and reliability. Indeed, electrical characteristics are controlled by the charge transport processes both along and across the nano-layers of adjacent materials; these processes are sensitive to atomic-level changes in the materials structure and composition that pose new challenges for analyzing device properties. Pre-existing (as-fabricated) defects not only affect initial values of device parameters but may also dominate their time dependency (reliability): trapping of injected charge carriers by pre-existing defects shifts device parameters with time and activates charge transport via these defects that is recorded as leakage current through the dielectric stack. Generation of additional defects is associated with structural changes requiring sufficiently high local electric field and/or temperature on longer time scales; consequently, defect generation requires higher voltages, ambient temperature, lower switching frequency, etc. that may not be available under operation conditions. The above considerations indicate that electrical and reliability characteristics are extremely sensitive to test conditions. In particular, a conventional higher voltage accelerated stress, widely employed to reduce test time, can cause defect generation, which does not occur under lower voltages employed in operation conditions. That leads to overly conservative reliability assessment and underestimation of device lifetime. On the other hand, DC and low frequency pulse measurements miss fast charging/discharging processes, leading to underestimation of the parameters shift occurring in high frequency circuit operations. Degradation mechanisms behind the proposed application-specific reliability test approach, which was demonstrated on a variety of devices, can be understood using electric field-induced defect generation and charge transport modeling results. Application-specific testing defines the safe range of use-conditions that may significantly extend device lifetime beyond the limits provided by conventional methods,
Gennadi Bersuker, Donald Pierce, and Maribeth Mason, "Devices in advanced technology nodes: Application-specific characterization" in "International Conference on Semiconductor Technology for Ultra-Large Scale Integrated Circuits and Thin Film Transistors VI (ULSIC vs TFT 6)", Yue Kuo (Texas A&M University, USA) Olivier Bonnaud (University of Rennes I, France) Eds, ECI Symposium Series, (2017). http://dc.engconfintl.org/ulsic_tft_6/18
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