Title
Terahertz testing of very large scale integrated circuits
Conference Dates
May 19-23, 2019
Abstract
Growing sophistication of electronics devices and circuits and, especially of VLSI and ULSIC, presents increasing demands on circuit testing and fault diagnosis. The conventional well-established technique of electric AC and DC testing is costly, does not assure a complete fault identification. This technique also presents an additional security problem making it possible to design faked circuits avoiding the identification by this testing.1 Fabrication of and even perception of faked VLSI capable of surreptitious performance has become an increasing problem often referred to as “trojan hardware”. Experimental techniques, such as laser scanning2and terahertz imaging 3-5 have a limited resolution signal-to-noise ratios and encounter difficulties in defect identification. A new approach of THz testing of Microwave Monolithic Integrated Circuits (MMICs)6, VLSI, and ULSIC is based on measuring the circuit responses at the pins or input/output leads and comparing these responses with etalon responses. 7, 8 This technique could augment or replace the electrical testing and/or laser and THz scanning testing for production testing, burn-in testing, high temperature testing, and infant mortality testing. It could also be extended for the fault diagnosis and identification and for the lifetime and reliability predictions. To this end it could be augmented by the low noise measurements. The number of the detected responses could be very large, since the permutations of the voltages between the pins and leads could be measured at the different positions of the scanning THz beam, different THz frequencies and polarizations, in the pulsed and/or CW mode, at the different modulation frequencies and at the different THz intensities. This technique could be used under or without bias. The processing of these responses forming multi-dimensional images in the excitation parameter space could be processed using artificial intelligence algorithms and machine learning approaches making this testing technique self-learning and self-improving. This testing could be further improved by designing for testability by THz responses at the pins.
Acknowledgements The work at RPI was supported by the U.S. Army Research Laboratory Cooperative Research Agreement (Project Monitor Dr. Meredith Reed) and by the Office of Naval Research (Project Monitor Dr. Paul Maki).
References
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7. G. Rupper, J. Suarez, S. Rudin, M. Reed, M. Shur, Terahertz plasmonics for testing very large-scale integrated circuits under bias, Patent Application Publication, No.: US 2018/0238961 Al, Pub. Date: Aug. 23, 2018
8. M. Shur, S. Rudin, G. Rupper, M. Reed, and J. Suarez, Sub-Terahertz Testing of Millimeter Wave Monolithic and Very Large Scale Integrated Circuits, Solid State Electronics (2019), to be published
Recommended Citation
M. Shur and J. Suarez, "Terahertz testing of very large scale integrated circuits" in "Semiconductor Technology for Ultra Large Scale Integrated Circuits and Thin Film Transistors VII (ULSIC VS TFT 7)", Yue Kuo, Texas A&M University, USA Junichi Murota, Tohoku University, Japan Yukiharu Uraoka, Nara Advanced Institute of Science and Technology, Japan Yasuhiro Fukunaka, Kyoto University, Japan Eds, ECI Symposium Series, (2019). https://dc.engconfintl.org/ulsic_tft_vii/51