Invited; An overview of the three-dimensionally stacked dynamic random access memory

Conference Dates

May 15-18, 2023


As the DRAM scaling proceeds, challenges related to device integration are becoming overwhelming. The challenges include securing the cell transistor performance, cell capacitance, and low wire resistance. The current two-dimensional integration will meet a significant barrier for further device integration near the design rule of ~ 10nm, which will happen within the next ten years. The die-stacking technology, making the highbandwidth memory, is an alternative approach but lacks cost-competitiveness. Therefore, cell-stacking technology will be needed for the higher-density DRAM fabrication up to tera-bit, which has been implemented in the vertical-NAND flash. However, DRAM requires a much higher cell transistor performance than the NAND flash, where the polycrystalline Si could meet cell transistor requirements.

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