Title
Instability mechanisms in amorphous oxide semiconductors leading to a threshold voltage shift in thin film transistors
Conference Dates
May 21-25, 2017
Abstract
Amorphous oxide semiconductors (AOSs) have emerged as the leading alternative to silicon thin film materials for the channel layer in thin film transistors (TFTs) [1]. A key reason for this is that TFTs fabricated using AOSs, such as amorphous indium gallium zinc oxide (a-IGZO) or amorphous zinc tin oxide (a-ZTO), have a much higher field-effect mobility than amorphous silicon. However, like amorphous silicon, under some circumstances AOS TFTs suffer from a threshold voltage shift upon application of a gate bias [2, 3]. This is a significant problem if the devices are to be used to control active matrix displays, such as those based on organic light emitting diodes where it is desired to accurately control the current through the diode using the gate voltage applied to a TFT, or in logic circuits. There have been many studies of both positive and negative bias stress effects in AOS TFTs [4]. The types of bias stress instability that are observed strongly depend on the structure of the TFT, and in particular on the choice of gate dielectric, as this can lead to instability caused by charge trapping in the dielectric or at the dielectric-channel interface. However, even when these effects are negligible, bias stress instability is still observed due to processes taking place in the AOS channel material itself. In previous work, we have used the concept of a thermalization energy to analyze positive and negative bias stress data from AOS TFTs based on zinc oxide (a-IGZO and a-ZTO) [2, 3, 5]. Using on this and other known properties of these semiconductors, we have identified five experimental observations that any model for the microscopic process underlying the bias stress effect in these materials must satisfy: 1. a negative shift in the threshold voltage occurs for negative gate bias and a positive shift occurs for positive gate bias; 2. illumination with light is required to induce a negative threshold voltage shift, whereas positive threshold voltage shifts occur both with and without illumination; 3. the threshold voltage shift is metastable, and the rate of shift is strongly temperature-dependent in the range from room temperature up to ~400 K when structural changes are not occurring; 4. the energy barrier to the instability mechanism is ~0.75 eV; and 5. there is an attempt-to-escape frequency of ~107 s–1 associated with the instability process. Based on this, we have proposed such a microscopic model where the underlying process is oxygen vacancy migration which can produce a change in the equilibrium distribution of defect states in the semiconductor band gap when the quasi-Fermi energy changes as a result of the application of a gate bias and/or illumination with photons. This leads to the observed shift in the threshold voltage [5]. The support of this work by the Engineering and Physical Sciences Research Council (EPSRC) through project EP/M013650/1 is acknowledged. [1] E. Fortunato, P. Barquinha, and R. Martins, "Oxide Semiconductor Thin-Film Transistors: A Review of Recent Advances," Advanced Materials, vol. 24, pp. 2945-2986, Jun 2012. [2] K. M. Niang, P. M. C. Barquinha, R. F. P. Martins, B. Cobb, M. J. Powell, and A. J. Flewitt, "A thermalization energy analysis of the threshold voltage shift in amorphous indium gallium zinc oxide thin film transistors under positive gate bias stress," Applied Physics Letters, vol. 108, p. 093505, 2016. [3] K. M. Niang and A. J. Flewitt, "Stability under Gate Bias Stressing of Amorphous Oxide Thin Film Transistors," ECS Transactions, vol. 75, pp. 179-187, August 18, 2016 2016. [4] J. F. Conley, "Instabilities in amorphous oxide semiconductor thin film transistors," Transactions on Device and Materials Reliability, vol. 10, pp. 460-475, 2010. [5] A. J. Flewitt and M. J. Powell, "A thermalization energy analysis of the threshold voltage shift in amorphous indium gallium zinc oxide thin film transistors under simultaneous negative gate bias and illumination," Journal of Applied Physics, vol. 115, pp. 134501.1-134501.7, 2014.
Recommended Citation
Andrew J. Flewitt and Kham M. Niang, "Instability mechanisms in amorphous oxide semiconductors leading to a threshold voltage shift in thin film transistors" in "Semiconductor Technology for Ultra-Large Scale Integrated Circuits and Thin Film Transistors VI (ULSIC vs TFT 6)", Yue Kuo (Texas A&M University, USA) Olivier Bonnaud (University of Rennes I, France) Eds, ECI Symposium Series, (2017). https://dc.engconfintl.org/ulsic_tft_6/3