Title
Two-terminal vertical thyristor-based capacitorless memory cells using latch-up features
Conference Dates
May 21-25, 2017
Abstract
Conventional dynamic random access memory (DRAM) has been facing a severe challenge to scale down the capacitor because the cell capacitor should be able to store sufficient charges of 25~30 fF/cell. Many kinds of emerging devices have been proposed to overcome this challenge coming from capacitor; i.e., ReRAM, CBRAM, PRAM, and STT-MRAM. However, the vertical thyristor based two-terminal capacitorless memory is a candidate to replace current DRAM, which consists of only one p++n+p+n++ vertical structure diode using conventional Si technology. The two-terminal vertical thyristor based capacitorless memory cell having p++(anode)n+(n-base)p+(p-base)n++(cathode) structure is easily able to construct cross-point memory array-cells, as shown in Figure 1. It utilizes latch-up characteristics showing bi-stable current-voltage (I-V) characteristics, which are generated by n+p+ base region under an applied bias. However, the demonstration of the device has not been successfully performed yet because of its difficult device fabrication process (i.e., dopant fluctuation at the p/n junction interface, presence of dislocations & stacking faults depending on dopant concentration). In our study, the dependency of the latch-up characteristics (i.e., bi-stability, Ion/Ioff ratio) on dopant concentration and thickness of n+p+ base were investigated by performing simulations, as shown in Figure 2. I-V characteristics in Fig. 2 exhibited that latch-up voltage increased with the dopant concentration of n+p+ base, while the latch-up characteristic was not established at dopant concentration of 1 x 1017 cm-3. It was confirmed that the latch-up voltage increasing with dopant concentration of n+p+ base region was associated with the hole and electron diffusion barrier in n+p+ base region. In addition, the latch-up voltage was in detail investigated as a function of the n+(n-base)p+(p-base) concentration independently. Furthermore, we will review the device physics of this memory cell and demonstrate memory cell operation.
Please click Additional Files below to see the full abstract.
Recommended Citation
Min-Won Kim, Tae-Hun Shim, Seung-Hyun Song, Sang-Dong Yoo, and Jea-Gun Park, "Two-terminal vertical thyristor-based capacitorless memory cells using latch-up features" in "Semiconductor Technology for Ultra-Large Scale Integrated Circuits and Thin Film Transistors VI (ULSIC vs TFT 6)", Yue Kuo (Texas A&M University, USA) Olivier Bonnaud (University of Rennes I, France) Eds, ECI Symposium Series, (2017). https://dc.engconfintl.org/ulsic_tft_6/6