Investigation of degradation caused by charge trapping at etching-stop layer under AC gate-bias stress for InGaZnO thin film transistors
May 19-23, 2019
A great amount of literatures has been focusing on bias-induced instability issues including threshold voltage shift (ΔVt ) and subthreshold swing (S.S) degradations . However, in practical TFT operation circuits, very limited knowledge could be applied since operation modes are mostly applied with alternative current (AC). Based on these backgrounds, in this work, Indium-Gallium-Zinc-Oxide Thin Film Transistors (IGZO TFTs) are applied with AC PBS degradations. Compared with previous work, this work observed a structure dependent degradation. An etch-stop structure IGZO TFT observed a serious threshold voltage shift after AC stress but shown great stability after direct current (DC) stress. The device structure and transfer characteristic curves are demonstrated in Figure 1(a) and (b) respectively. From results of DC PBS/NBS, a favorable stability indicating a great quality of gate insulator. Therefore, the positive threshold voltage shift is believed to be origin from electron trapping at the etching stop layer (ESL), since ESL possesses a relatively poor quality compared to the gate insulator. The charge trapping at etching stop layer could be confirmed by results of asymmetric source/drain metal under AC stress, illustrated in Figure 1(c).
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Mao-Chou Tai, Yu-Ching Tsao, Po-Wen Chang, and Mao-Chou Tai, "Investigation of degradation caused by charge trapping at etching-stop layer under AC gate-bias stress for InGaZnO thin film transistors" in "Semiconductor Technology for Ultra Large Scale Integrated Circuits and Thin Film Transistors VII", Yue Kuo, Texas A&M University, USA Junichi Murota, Tohoku University, Japan Yukiharu Uraoka, Nara Advanced Institute of Science and Technology, Japan Yasuhiro Fukunaka, Kyoto University, Japan Eds, ECI Symposium Series, (2019). https://dc.engconfintl.org/ulsic_tft_vii/12