Device layout dependence of PBTI in back-gated IGZO TFTs

Conference Dates

May 15-18, 2023


The attractive electrical and processing properties of IGZO-based TFTs make these devices promising in various applications, but primarily in BEOL logic and DRAM cells [1,2]. IGZO has been shown to meet the performance requirements of many applications such as display and DRAM selectors [2]. However, the reliability of industry relevant gate-dielectric based IGZO devices has been only recently tackled [3,4]. In addition, the role of device layout and channel geometry (depending on the target application) has not been investigated. In this work we systematically study BTI degradation in 2 main families of back-gated IGZO transistors based on a 10nm thermally grown SiO2 as gate-dielectric, each one differing in S/D access geometry and/or channel width. In the first one, the S/D contacts have very large area with ~5000μm2 (M0 devices), while the second one is based on much smaller contact area of 135nm × device width W (M1 device) (Fig1, left). For each family, gate lengths Lg spanning 2 orders of magnitude (from ~200nm to ~30μm) are investigated to detect short channel effects. Vth0 is extracted at a fixed current level of 100pA×W/L for both architectures (Fig 1., middle). While M0 devices suffer from a decrease of Vth0 as a function of Lg, the Vth of M1 devices is very stable for all measured Lg.

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