Title
A TCAD calibrated approach for on-state modeling of amorphous oxide semiconductor TFTs
Conference Dates
May 19-23, 2019
Abstract
Amorphous oxide semiconductor materials such as IGZO exhibit electrical characteristics that are not well represented by conventional device models due to the presence of band-tail states (BTS). Common parameters such as threshold voltage and channel mobility that are extracted from measured electrical characteristics can be misrepresentative due to discrepancies between the device operation and the chosen operational model. Compact models that have been developed for model accuracy and circuit simulation efficiency offer limited insight on the underlying device physics involved. The focus of this work is a model for device engineering which maintains a close physical connection to device operation, and captures the 2D influence of both the gate and drain bias conditions on the ionization and deionization of acceptor-like BTS near the conduction band edge.
A device model for the on-state operation of accumulation-mode IGZO TFTs was recently presented as an adaptation of a Level 2 SPICE (L2S) model [1]. The model introduced channel charge adjustments which account for the occupancy of BTS as influenced by the gate and drain voltage, and provided an exceptional match to both simulated and measured device characteristics. However the integrity of the model as assessed by the ability to discriminate between the influence of BTS and short-channel effects (SCE) was compromised as the device channel length was decreased. Accumulation-mode devices are susceptible to the onset of SCE at relatively long channel lengths due to the lack of a source-channel junction barrier. While the subthreshold region may show minimal influence of drain induced barrier lowering (DIBL), the on-state may exhibit an effective decrease in the triode region of operation.
A new model is presented which incorporates this on-state DIBL along with channel length modulation, and demonstrates improved discrimination between BTS and SCE in the model fit at device channel lengths L ≥ 3 µm. Silvaco® Atlas™ TCAD played a key role in device model development. A long-channel reference device was used to establish the impact of SCE on short devices, which was then modeled by and terms in associated triode and saturation regions of operation. For channel lengths L < 3 µm, a lumped SCE multiplier was used to represent short-channel behavior, followed by the application of BTS parameters for channel charge adjustments. Modeling results derived from both simulated and measured TFT characteristics will be presented.
[1] K.D. Hirschman, T. Mudgal, E. Powell and R.G. Manley, ECS Trans. 86, 153 (2018)
Recommended Citation
Karl Hirschman, Glenn Packard, and Robert Manley, "A TCAD calibrated approach for on-state modeling of amorphous oxide semiconductor TFTs" in "Semiconductor Technology for Ultra Large Scale Integrated Circuits and Thin Film Transistors VII (ULSIC VS TFT 7)", Yue Kuo, Texas A&M University, USA Junichi Murota, Tohoku University, Japan Yukiharu Uraoka, Nara Advanced Institute of Science and Technology, Japan Yasuhiro Fukunaka, Kyoto University, Japan Eds, ECI Symposium Series, (2019). https://dc.engconfintl.org/ulsic_tft_vii/5